1. Field of the Invention
The present invention relates to direct digital frequency synthesizers and more particularly to fractional divider direct digital frequency synthesizers.
2. Description of Related Art
Frequency synthesizers comprise important building blocks in precise time and frequency systems. Direct digital synthesizers (DDSs) which digitally synthesize waveforms without the use of phaselock techniques have become increasingly important due to the advent of large scale integrated circuits. Through the use of monolithic fabrication techniques, relatively small DDSs can be built which feature relatively high and easily expandable frequency resolutions, wide frequency ranges and short settling times.
Two important earlier types of DDSs are the pulse output DDS and the fractional divider DDS. These earlier DDSs together with other earlier DDSs are discussed in "Direct Digital Synthesizers" by Victor S. Reinhardt, Proceedings of the 17th Annual Precise Time and Time Interval Applications and Planning Meeting (NASA/DOD), Washington, D.C., Dec. 3-5, 1985.
Referring to FIG. 1, there is shown a block diagram of a typical earlier pulse output DDS (10). The pulse output DDS (10) includes an N-bit storage accumulator (12) and an N-bit adder (14) connected as shown. The N-bit adder (14) adds the frequency word k to the value in the storage accumulator (12) once during each clock period of a clock signal characterized by a clock frequency f.sub.c. The N-bit adder (14) performs the addition in modulo 2.sup.N arithmetic such that the adder (14) will generate a carry bit on average once every 2.sup.N /k clock periods. The pulse output signal, which is characterized by a frequency f.sub.o, comprises a train of pulses corresponding to a sequence of carry bits from the adder (14). Thus, the average output frequency is the average frequency of accumulator overflows which is f.sub.c .multidot.k/2.sup.N.
Referring to FIG. 2, there is shown a block diagram of a typical earlier fractional divider DDS (20). The earlier fractional divider DDS (20) includes an N-bit accumulator (22) and a divide by n/n+1 counter (24) connected as shown. The counter (24) receives an input clock signal characterized by a clock frequency f.sub.c and provides an output signal characterized by an output frequency f.sub.o. The accumulator (22) is clocked by the output signal such that the contents of the accumulator (22) are incremented by the frequency word k each time an output signal pulse is provided. The counter (24) performs division by n unless an accumulator carry bit is generated. Whereupon, the counter (24) receives a signal on line (26) causing it to perform division by n+1. The average output frequency f.sub.o is f.sub.c /(n+F); where F=k/2.sup.N.
A problem with earlier pulse output DDSs and fractional divider DDSs of the general types described above is that the output signals produced are characterized by frequency spectrums which contain a relatively high level of spurious sidebands (spurs) when the respective value of F is not an inverse power of two. These spectral spurs occur because accumulator overflows (transitions) deviate in time (transition jitter) from that of an ideal frequency generator at an output frequency f.sub.o, and because the deviations in transition time form a periodic pattern whose period is equal to some multiple of the clock period T.sub.c. Hence, the periodic pattern produces a coherent frequency spectrum characterized by the spurious sidebands.
Wheately III in U.S. Pat. No. 4,410,954 which issued on Oct. 18, 1983 discloses a random jitter technique for reducing the size of spectral spurs produced by certain DDSs. His technique reduces such spurs by substantially destroying the periodicity of the accumulator overflows. In one embodiment, the technique comprises the steps of successively replacing the frequency word k by random words k+x.sub.i ; and by k-x.sub.i ; where .vertline.x.sub.i .vertline. represents a sequence of equally distributed random values from 0 to k-1. According to Wheately III, this technique eliminates spurious sidebands without detriment to the average output frequency.
While earlier DDSs generally have been successful, there have been limitations associated with their use. For example, although the technique proposed by Wheately III substantially reduces spurious sidebands, it achieves this result through relatively complex circuitry which is used to generate values .vertline.x.sub.i .vertline.. This is because the properties of the substituted random word change with the synthesized output frequency. More particularly, the output frequency f.sub.o depends upon the value of k, and since typical DDSs must be capable of generating a plurality of output frequencies, the value of k must be variable. However, the value of .vertline.x.sub.i .vertline. must vary uniformly between 0 and k-1. Consequently, relatively complex circuitry must be provided for providing a random value .vertline.x.sub.i .vertline. which varies uniformly between 0 and k-1, where the value of k is variable.
Thus, there has been a need for a DDS which is characterized by an output signal having a frequency spectrum with substantially no spurious sidebands and which can be implemented using relatively simple circuitry. The present invention meets this need.